To meet the demand for wireless data traffic having increased since deployment of 4G (4th-Generation) communication systems, efforts have been made to develop an improved 5G (5th-Generation) or pre-5G communication system. Therefore, the 5G or pre-5G communication system is also called a ‘beyond 4G network’ or a ‘post LTE system’.
The 5G communication system is considered to be implemented in higher frequency (mmWave) bands, e.g., 60 GHz bands, so as to accomplish higher data rates. To decrease propagation loss of the radio waves and increase the transmission distance, the beamforming, massive multiple-input multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, an analog beam forming, large scale antenna techniques are discussed in 5G communication systems.
In addition, in 5G communication systems, development for system network improvement is under way based on advanced small cells, cloud radio access networks (RANs), ultra-dense networks, device-to-device (D2D) communication, wireless backhaul, moving network, cooperative communication, coordinated multi-points (CoMP), reception-end interference cancellation and the like.
In the 5G system, hybrid FSK and QAM modulation (FQAM) and sliding window superposition coding (SWSC) as an advanced coding modulation (ACM), and filter bank multi carrier (FBMC), non-orthogonal multiple access (NOMA), and sparse code multiple access (SCMA) as an advanced access technology have been developed.
FIG. 1 schematically illustrates an inner structure of a signal receiving apparatus in a conventional communication system supporting an LDPC code.
Referring to FIG. 1, the signal receiving apparatus in FIG. 1 is a signal receiving apparatus including replicated group-shuffled sub-decoders, and this will be described.
The signal receiving apparatus includes a sub-decoder #1 110, a sub-decoder #2 120, and a sub-decoder #3 130. Each of the sub-decoder #1 110, the sub-decoder #2 120, and the sub-decoder #3 130 includes three bit groups. That is, the sub-decoder #1 110 includes a bit group #1 111, a bit group #2 113, and a bit group #3 115, the sub-decoder #2 120 includes a bit group #1 121, a bit group #2 123, and a bit group #3 125, and the sub-decoder #3 130 includes a bit group #1 131, a bit group #2 133, and a bit group #3 135.
In FIG. 1, bit groups used in each of the sub-decoder #1 110, the sub-decoder #2 120, and the sub-decoder #3 130 are identical, however, update orders used in each of the sub-decoder #1 110, the sub-decoder #2 120, and the sub-decoder #3 130 are different.
In the sub-decoder #1 110, bit estimates included in the bit group #1 111 are updated in the first repeat sub-step, bit estimates included in the bit group #2 113 are updated in the second repeat sub-step, and bit estimates included in the bit group #3 115 are updated in the third repeat sub-step.
In the sub-decoder #2 120, bit estimates included in the bit group #2 123 are updated in the first repeat sub-step, bit estimates included in the bit group #3 125 are updated in the second repeat sub-step, and bit estimates included in the bit group #1 121 are updated in the third repeat sub-step.
In the sub-decoder #3 130, bit estimates included in the bit group #3 135 are updated in the first repeat sub-step, bit estimates included in the bit group #1 131 are updated in the second repeat sub-step, and bit estimates included in the bit group #2 133 are updated in the third repeat sub-step.
That is, the signal receiving apparatus in FIG. 1 divides input bits into lower groups which have the same size which is less than the number of columns included in a parity check matrix for the LDPC code used in the communication system, i.e., a column size to perform a decoding operation in three sub-decoders. In this case, each of the sub-decoder #1 110, the sub-decoder #2 120, and the sub-decoder #3 130 needs a “message from a variable node to a check node (variable-to-check message)” in order to update a “message from a check node to a variable node (check-to-variable message)”.
As such, the signal receiving apparatus needs many memory read/write operations in order to read/write messages from/to a memory or a register.
If the communication system is an application system which needs a high data processing rate, the signal receiving apparatus should use many memory banks.
As such, a shuffled LDPC decoding algorithm needs a variable-to-check message which is lastly updated and variable-to-check messages which are just before updated, and the signal receiving apparatus consumes much power due to a structure which performs a memory read/write operation and has a storage device corresponding to this.
The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present disclosure.